Data Type
A data type (known as a subtype indication in the VHDL standard) appears in
a declaration to identify the type used at that point. A data type can also
include a constraint, which further restricts the values of the type during
simulation or synthesis. A data type can also include the name of a resolution
function to define the behaviour of a bus when there are conflicts between the
drivers. The resolution function is called by the simulator whenever a signal is
assigned.
Syntax
[ResolutionFunctionName] TypeName [Constraint]
Constraint = {either}
range Range {range constraint}
(Range, ...) {index constraint}
Rules
The constraint must be consistent with the type; range constraint for an
integer, floating, enumeration or physical type, index constraint for an
unconstrained array type.
If the value goes outside the constraint during simulation, this is an error and
simulation halts with the message "Constraint Violation".
Things to remember
Signals and variables cannot be unconstrained arrays. You must remember
the index constraint.
A resolution function should be written such that is independent of the order of
its inputs; otherwise, the results of simulation will be indeterminate!
Synthesis
Resolution functions are ignored by most synthesis tools.
Both range and index constraints are used to determine the widths of busses.
Example
BOOLEAN -- no constraint
INTEGER range 0 to 255
STD_LOGIC_VECTOR(7 downto 0)
RESOLVED STD_ULOGIC -- resolution function
See Also
Type, Signal, Disconnect, Subtype, Range, Function
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